module HexDisp(clk, lock, abus, dbus, we, out, blink_out);
	parameter BITS;
	parameter ADDRDATA;
	parameter ADDRBLNK;
	parameter CLOCKS_PER_MS;
	
	input clk, lock;
	input [31:0] abus;
	inout [31:0] dbus;
	input we;
	output [(BITS-1):0] out;
	output blink_out;
	
	reg [31:0] blink_interval, blink_count;
	reg [(BITS-1):0] HexOut;
	reg blink;
	
	wire sigms = (count_to_ms >= (CLOCKS_PER_MS-1));
	reg [31:0] count_to_ms;
	
	wire selData = (abus == ADDRDATA);
	wire selBlnk = (abus == ADDRBLNK);
	wire wrData = selData && we;
	wire wrBlnk = selBlnk && we;
	wire rdData = selData && !we;
	wire rdBlnk = selBlnk && !we;
	wire reset = !lock;
	
	always @(posedge clk or posedge reset) begin
		if (reset) begin
			HexOut <= {BITS{1'b0}};
			blink_interval <= 32'b0;
			blink_count <= 32'b0;
			blink <= 1'b0;
		end
		else begin
			if (sigms) begin
				blink_count <= blink_count + 1;
				if (blink_count == (blink_interval-1)) begin
					blink_count <= 32'b0;
					blink <= !blink;
				end
			end
			
			if (wrData) begin
				HexOut <= dbus[(BITS-1):0];
			end
			else if (wrBlnk) begin
				blink_interval <= dbus;
				blink_count <= 32'b0;
			end
		end
	end
	
	always @(posedge clk or posedge reset) begin
		if (reset) begin
			count_to_ms <= 32'b0;
		end
		else begin
			if (sigms) begin
				count_to_ms <= 32'b0;
			end
			else begin
				count_to_ms <= count_to_ms + 1;
			end
		end
	end

	assign dbus = rdData ? {{(32-BITS){1'b0}},HexOut} :
						rdBlnk ? blink_interval :
						{32{1'bZ}};
	assign out = HexOut;
	assign blink_out = (blink_interval) ? blink : 1'b0;

endmodule